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THC63LVD104A Rev.1.0
THine
THC63LVD104A
90MHz 30Bits COLOR LVDS Receiver
General Description
The THC63LVD104A receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to WXGA resolutions. The THC63LVD104A converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or falling edge clock for convenient with a variety of LCD panel controllers.At a transmit clock frequency of 90MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 630Mbps per LVDS channel.Using a 90MHz clock, the data throughput is 394Mbytes per second.
Features
* Wide dot clock range: 8-90MHz suited for NTSC,
VGA, SVGA, XGA, and WXGA
* * * * * * *
PLL requires no external components 50% output clock duty cycle TTL clock edge programmable Power down mode Low power single 3.3V CMOS design 64pin TQFP Backward compatible with THC63LVDF64x (18bits) / F84x(24bits)
Block Diagram LVDS INPUT
RA+/SERIAL TO PARALLEL RB+/RC+/RD+/RE+/RCLK+/(8 to90MHz)
CMOS/TTL OUTPUT
7 7 7 7 7 PLL RA6-RA0 RB6-RB0 RC6-RC0 RD6-RD0 RE6-RE0 CLKOUT
CMOS/TTL INPUT
TEST PD OE R/F
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Pin Out
RARA+ RBRB+ LVCC RCRC+ RCLKRCLK+ LGND RDRD+ RERE+ PGND PVCC
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCC RA0 RA1 RA2 GND RA3 RA4 RA5 RA6 RB0 RB1 VCC RB2 RB3 RB4 RB5
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
RB6 CLKOUT GND RC0 RC1 RC2 RC3 RC4 RC5 VCC RC6 RD0 RD1 RD2 RD3 RD4
Copyright 2003 THine Electronics, Inc. All rights reserved
GND TEST PD OE R/F RE6 RE5 RE4 VCC RE3 RE2 RE1 RE0 RD6 RD5 GND
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Pin Description
Pin Name RA+, RARB+, RBRC+, RCRD+, RDRE+,RERCLK+, RCLKRA6 ~ RA0 RB6 ~ RB0 RC6 ~ RC0 RD6 ~ RD0 RE6 ~ RE0 TEST PD OE R/F VCC CLKOUT GND LVCC LGND PVCC PGND Pin # 50, 49 52, 51 55, 54 60, 59 62, 61 57, 56 40,41,42,43,45,46,47 32,33,34,35,36,38,39 22,24,25,26,27,28,29 14,15,17,18,19,20,21 6,7,8,10,11,12,13 2 3 4 5 9,23,37,48 31 1,16,30,44 53 58 64 63 Type LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN OUT OUT OUT OUT OUT IN IN IN IN Power OUT Ground Power Ground Power Ground Test pin, must be "L" for normal operation. H: Normal operation, L: Power down (all outputs are "L") H:Output enable (Normal operation). L:Output disable(all outputs are Hi-Z) Output Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL outputs and digital circuitry. Clock out. Ground Pins for TTL outputs and digital circuitry. Power Supply Pin for LVDS inputs. Ground Pin for LVDS inputs. Power Supply Pin for PLL circuitry. Ground Pin for PLL circuitry. CMOS/TTL Data Outputs. LVDS Clock In. LVDS Data In. Description
PD 0 0 0 0 1 1 1 1 ** Rxn x = A,B,C,D,E n = 0,1,2,3,4,5,6
R/F 0 0 1 1 0 0 1 1
OE 0 1 0 1 0 1 0 1
Data Outputs (Rxn) Hi-Z All 0 Hi-Z All 0 Hi-Z Data Out Hi-Z Data Out
CLKOUT Hi-Z Fixed Low Hi-Z Fixed Low Hi-Z It latches output data on falling edge. Hi-Z It latches output data on rising edge.
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Absolute Maximum Ratings 1
Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Output Current Junction Temperature Storage Temperature Range Resistance to soldering heat Maximum Power Dissipation @+25 C -0.3V ~ +4.0V -0.3V ~ (V CC + 0.3V) -0.3V ~ (V CC + 0.3V) -0.3V ~ (V CC + 0.3V) -30mA ~ 30mA +125 C -55 C ~ +125 C +260 C /10sec 1.0W
Electrical Characteristics CMOS/TTL DC Specifications
VCC = 3.0V ~ 3.6V, Ta = 0 C ~ +70 C Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage IOH= -4mA (data) IOH= -8mA (clock) IOL= 4mA (data) IOL= 8mA (clock)
0V V IN V CC
Conditions
Min. 2.0 GND 2.4
Typ.
Max. VCC 0.8
Units V V V
VOL IINC
Low Level Output Voltage Input Current
0.4 10
V A
LVDS Receiver DC Specifications
VCC = 3.0V ~ 3.6V, Ta = 0 C ~ +70 C Symbol VTH VTL IINL Parameter Differential Input High Threshold Differential Input Low Threshold Input Current Conditions VOC= 1.2V VOC= 1.2V VIN= 2.4V / 0V VCC= 3.6V -100 20 Min. Typ. Max. 100 Units mV mV A
1. "Absolute Maximum Ratings" are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
Copyright 2003 THine Electronics, Inc. All rights reserved 4 THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
VCC = 3.0V ~ 3.6V, Ta = 0 C ~ +70 C
Supply Current
Symbol IRCCG Parameter Receiver Supply Current (Gray Scale Pattern) Receiver Supply IRCCW Current (Checker Pattern) IRCCS Receiver Power Down Supply Current PD = L fCLKOUT = 90MHz fCLKOUT = 90MHz Conditions CL=8pF, Vcc=3.3V CL=8pF, Vcc=3.3V Typ. 70 Max. Units mA
112
mA
10
A
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Incremental Pattern(Gray Scale)
CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6
x=A,B,C,D,E
Toggle Pattern(Checker) CLKOUT Rx0 Rx1 Rx2 Rx3 Rx4 Rx5 Rx6
x=A,B,C,D,E
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
VCC = 3.0V ~ 3.6V, Ta = 0 C ~ +70 C
Switching Characteristics
Symbol tRCP Parameter CLKOUT Period Min. 11.1 Typ. T Max. 125.0 Units ns
tRCH tRCL tRS tRH tTLH tTHL tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2 tRPLL tRCIP
CLKOUT High Time CLKOUT Low Time TTL Data Setup to CLKOUT TTL Data Hold from CLKOUT TTL Low to High Transition Time TTL High to Low Transition Time Input Data Position0 Input Data Position1 Input Data Position2 Input Data Position3 Input Data Position4 Input Data Position5 Input Data Position6 Phase Lock Loop Set CLKIN Period 11.1 -0.25
t RCIP ------------ - 0.25 7 t RCIP 2 ------------ - 0.25 7 t RCIP 3 ------------ - 0.25 7 t RCIP 4 ------------ - 0.25 7 t RCIP 5 ------------ - 0.25 7 t RCIP 6 ------------ - 0.25 7
T-1 ----------2 T-1 ----------2
ns ns ns ns
tRCP - 7.0 1.0 1.0 1.0 0.0
t RCIP -----------7 t RCIP 2 -----------7 t RCIP 3 -----------7 t RCIP 4 -----------7 t RCIP 5 -----------7 t RCIP 6 -----------7
2.0 2.0 +0.25
tRCIP ------------ + 0.25 7 t RCIP 2 ------------ + 0.25 7 t RCIP 3 ------------ + 0.25 7 t RCIP 4 ------------ + 0.25 7 t RCIP 5 ------------ + 0.25 7 t RCIP 6 ------------ + 0.25 7
ns ns ns ns ns ns ns ns ns ms ns
10.0 125.0
AC Timing Diagrams TTL Outputs
TTL Output CL=8pF 20% 20% 80% 80%
TTL Output Load tTLH tTHL
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
AC Timing Diagrams TTL Outputs
tRCH tRCL R/F = L
CLKOUT
2.0V
2.0V
2.0V
0.8V tRCP tRS 2.0V 0.8V tRH
0.8V R/F = H
Rxn
2.0V 0.8V
x = A,B,C,D,E n = 0,1,2,3,4,5,6
Phase Lock Loop Set Time
VCC
3.0V
RCLK+/-
PD
2.0V
tRPLL 2.0V
CLKOUT
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Power Up Sequence
Power Up Sequence must be Sequence1 or Sequence2. 1)Sequence1
VCC PVCC LVCC
VCC/2
Min 100usec
PD
VCC/2
Recommended PD Pin Circuit
VCC
100kohm
PD Pin 0.1uF
2)Sequence2
VCC PVCC LVCC
3.0V
VCC
GND
VCC
PD
GND
GND
PD pin must be High after VCC voltage is 3.0V.
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
AC Timing Diagrams LVDS Inputs
tRIP2 tRIP3 tRIP4 tRIP5 tRIP6 tRIP0 tRIP1
Rx+/-
Rx6
Rx5
Rx4
Rx3
Rx2
Rx1
Rx0
Rx6
Rx5
Rx4
Rx3
Rx2
Rx1
RCLK+
Vdiff = 0V
Vdiff = 0V
x = A,B,C,D,E
tRCIP
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
AC Timing Diagrams LVDS Inputs
Vdiff = 0V Vdiff = 0V
RCLK+ (Differential) RA+/RA3' RA2' RA1' RA0' RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA6''
RB+/-
RB3' RB2'
RB1' RB0'
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RB6''
RC+/-
RC3' RC2'
RC1' RC0'
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RC6''
RD+/-
RD3' RD2' RD1' RD0'
RD6
RD5
RD4
RD3
RD2
RD1
RD0 RD6''
RE+/-
RE3'
RE2'
RE1'
RE0'
RE6
RE5
RE4
RE3
RE2
RE1
RE0
RE6''
Previous Cycle
Current Cycle
Next Cycle
tRIP1 tRIP0 tRIP6 tRIP5 tRIP4 tRIP3 tRIP2
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Package
INDEX
64
49
PIN No.1 0.5TYP
48
0.22
16
33
17
32
1.00TYP
1.2MAX
UNITS: mm
Copyright 2003 THine Electronics, Inc. All rights reserved
12
10.0TYP
12.0TYP
THine Electronics, Inc.
THC63LVD104A Rev.1.0
THine
Notes to Users:
1. The contents of this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention when designing circuits. EVEN IF THERE ARE INCORRECT DESCRIPTIONS, THINE IS NOT RESPOSIBLE FOR ANY PROBLEM DUE TO THEM. Please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. THine's copyright, know-how and other intellectual property rights are included in this data sheet. Duplication of the data sheet and disclosure to other persons are strictly prohibited without THine's prior written permission. 4. THINE IS NOT RESPONSIBLE FOR ANY PROBLEMS OF INTELLECTUAL PROPERTY RIGHTS OCCURRING DURING THC63LVD104A USE, EXCEPT FOR DAMAGES RESULTING FROM INFRINGEMENT CAUSED ONLY BY THC63LVD104A WITHOUT ANY ITEM NOT SOLD BY THINE AND/OR ANY USERS' ACTION. THINE IS NOT RESPONSIBLE FOR PROBLEMS CAUSED BY SPECIFICATIONS SUPPLIED BY USERS. THC63LVD104A is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people's lives, etc.). In addition, when using THC63LVD104A for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. THINE IS MAKING THE UTMOST EFFORT TO IMPROVE THE QUALITY AND RELIABILITY OF THINE'S PRODUCTS. HOWEVER, THERE IS A VERY SLIGHT POSSIBILITY OF FAILURE IN SEMICONDUCTOR DEVICES. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. No radiation-hardened design is incorporated in THC63LVD104A. 7. Judgment on whether THC63LVD104A comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user's responsibility. 8. This technical document was provisionally created during development of THC63LVD104A, so there is a possibility of differences between it and the product's final specifications. When designing circuits using THC63LVD104A, be sure to refer to the final technical documents.
THine Electronics, Inc. Wakamatsu Bldg, 6F 3-3-6, Nihombashi-Honcho, Chuo-ku, Tokyo, 103-0023 Japan Tel: 81-3-3270-0666 Fax: 81-3-3270-0688
Copyright 2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.

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